1. Field of the Invention
The present invention relates generally to memory management in computer systems, and more particularly to accelerating address translations following a translation lookaside buffer miss.
2. Description of Related Art
Virtual memory and the addresses used to locate information in the virtual memory is an old concept. Historically, virtual addresses were used to provide a large memory space to applications by a processor. The processor converted the virtual addresses to a physical address. To reduce the overhead in mapping a virtual address to a physical address, a translation lookaside buffer 100 (FIG. 1) was used.
Translation lookaside buffer 100 was a cache for holding recently used mappings from virtual addresses to physical addresses. Typically, a virtual address had two parts an offset and a virtual page identifier. The offset was the same for both the virtual address and the physical address.
Thus, the virtual address in FIG. 1 that was presented to translation lookaside buffer (TLB) 100 was the virtual page identifier. Translation lookaside buffer 100 checked to see if the virtual page identifier was stored in the cache and if it was, TLB 100 returned the physical address, which was the base address of the page in physical memory. However, if TLB 100 did not contain the virtual page identifier, a more detailed mapping was required using stored memory mapping tables and the TLB was updated as appropriate.
This approach was sufficient for a single operating system handling multiple applications, e.g., contexts. However, in main frames a further abstraction was introduced, e.g., virtual hardware.
As illustrated in FIG. 2, a plurality of operating systems 210_1, 210_2, e.g., different instances of the same operating system, or alternatively different operations systems, used a hardware processor 250. Each operating system supported a plurality of applications, e.g., operating system 210_1 supported applications 201_1, 201_2 and operating system 210_2 supported applications 202_1, 202_2.
In system 200, the hardware is logically partitioned. Logical partitioning allows multiple copies of a single operating system (OS) or multiple heterogeneous operating systems to simultaneously run on a single data processing system platform. A logical partition, within which an operating system image runs, is assigned a non-overlapping sub-set of the platform's resources. These platform allocable resources include one or more architecturally distinct processors with their interrupt management area, regions of system memory, and I/O adapter bus slots.
Hypervisor 210, typically implemented as firmware, performed a number of functions and services for operating systems 210_1, 210_2 to create and enforce the logical partitions. Hypervisor 210 owned all system resources and provided an abstraction layer through which device access and control was arbitrated.
Hypervisor 210 and firmware handled the mapping of memory, CPUs and adapters for each logical partition. Applications were generally unaware of where the partition's memory was located, which CPUs had been assigned, or which adapters were in use.
Each application had it owns virtual address space. The operating system associated with a particular application converted a virtual address to a real address. As far as the operating system was concerned the real address started at zero and went to a predetermined maximum value. Hypervisor 220 managed the physical memory addresses.
FIG. 3 is a conceptual illustration of a two-part translation lookaside buffer 300 that could be used in the translation from a virtual address to a physical address. A first table 310 includes mappings from virtual addresses to real addresses and a second table 320 includes mappings from real addresses to physical addresses.
However, TLB 300 required serialization and so typically, the logic equivalent of tables 310, 320 was implemented. In TLB 400, a first portion 401 was a field with a value that identified whether the address was a virtual address or a real address, a second portion 402 included either the virtual address or the read address, and a third portion 403 contained the mapping to the corresponding physical address. Thus, with TLB 400, it was possible to go directly from a virtual address to the corresponding physical address, or alternatively from a real address to the corresponding physical address.
An area of emphasis has been on how to minimize the penalty when there is a miss in TLB 400 for a virtual address. Two translations are required; one from the virtual to the real address; and one from the real address to the physical address. The second translation is the one that has received most of the attention.
Either the operating system, or the hypervisor using the operating system state can perform the virtual-to-real address translation. Typically, to do the translation from the real address to physical address translation base and bounds table, a coarse grain translation has been used.